1. Field of the Invention
The invention pertains generally to organic chip carriers for wire bond-type chips.
2. Description of the Related Art
Semiconductor integrated circuit devices (hereinafter referred to as semiconductor chips or just chips) are typically electronically packaged by mounting one or several chips onto a ceramic, e.g., alumina, chip carrier substrate and using wire bonds to electrically connect I/O (input/output) contact pads on each chip to corresponding contact pads (and therefore to corresponding fan-out circuitry) on the ceramic chip carrier substrate. The resulting ceramic chip carrier is then mounted onto a printed circuit board (PCB) or printed circuit card (PCC) and (via circuitry on the PCB or PCC) thereby electrically connected to other such ceramic chip carriers and/or other electronic components mounted on the PCB or PCC.
While the above-described packaging scheme is certainly useful, the use of ceramic chip carrier substrates does involve certain limitations and drawbacks. For example, as is known, the speed of propagation of an electrical signal through a wire on a dielectric layer, or between two dielectric layers, is proportional to the inverse of the square root of the dielectric constant of the dielectric layer or layers. Unfortunately, the dielectric constants of ceramics are relatively large, e.g., the dielectric constant of alumina is about 9, which results in ceramic chip carriers exhibiting relatively low, and in some cases undesirably low, signal propagation speeds.
The use of ceramic chip carrier substrates also leads to certain I/O constraints. For example, a single-layer ceramic chip carrier substrate includes but a single layer of fan-out circuitry on the upper surface of the single ceramic layer, extending to contact pads around the outer periphery of the single ceramic layer. (A lead frame, having inner leads connected to these peripheral contact pads, is typically used to electrically connect such a ceramic chip carrier to a PCB or PCC.) However, as the number of chip I/Os has increased, it has been necessary to increase the number of fan-out wires, and to correspondingly decrease the spacing between the fan-out wires, to the point where undesirable cross-talk between adjacent fan-out wires has become unacceptable. Moreover, it has become increasingly difficult, if not impossible, to form a correspondingly large number of contact pads around the outer periphery of the ceramic layer. Thus, single-layer ceramic chip carrier substrates are definitely limited in their ability to handle high I/O chips.
Attempts to accomodate chips having relatively large numbers of I/Os has led to the use of multilayer ceramic chip carrier substrates employing so-called ball grid arrays (BGAs) in lieu of lead frames. These types of ceramic chip carrier substrates differ from single-layer ceramic chip carrier substrates in that they include two or more layers of fan-out circuitry on two or more ceramic layers. Significantly, these layers of fan-out circuitry are electrically interconnected by mechanically drilled via holes, which are plated and/or filled with electrically conductive material. In addition, a certain number of such holes extend from the layers of fan-out circuitry to lands on the bottoms of the chip carrier substrates, on which are mounted solder balls (formed in grid arrays, hence the term ball grid array.) These solder balls are intended to be mechanically and electrically connected to corresponding solderable contact pads on a PCB or PCC. Unfortunately, the mechanically drilled holes electrically interconnecting the layers of fan-out circuitry have relatively large diameters, requiring the spacing between the fan-out wires to be relatively large. But, this relatively large spacing between fan-out wires limits the number of chip I/Os which can be accomodated by such multilayer ceramic chip carrier substrates.
Other attempts to package chips having a relatively large number of chip I/Os has led to the use of multi-tiered cavities in multi-layered ceramic substrates. (As used herein, the term "cavity" denotes a depression in a substrate, not a hole extending through the thickness of the substrate.) When using such a packaging configuration, a chip is mounted face-up at the bottom of a multi-tiered cavity. Wire bonds are extended from I/O contact pads on the upper surface of the chip to contact pads on each of the exposed upper surfaces of the different layers of the multi-layered ceramic substrate constituting the different tiers of the multi-tiered cavity. While this configuration does make it possible to accomodate a relatively large number of chip I/Os, it does result in relatively long wire bonds extending from the chip to the upper tiers of the multi-tiered cavity. As a consequence, the "time of flight" of corresponding electrical signals is undesirably increased.
Ceramic chip carrier substrates are also limited in terms of their heat dissipation capabilities. For example, in the case of a multilayer ceramic chip carrier having a chip positioned at the bottom of a multi-tiered cavity, heat dissipation is typically achieved by providing a heat sink directly beneath the cavity. But this implies that the heat generated by the chip must necessarily be conducted through the ceramic layer at the bottom of the cavity before reaching the heat sink. As a consequence, the rate of heat dissipation is limited.
Thus, those engaged in the development of chip carriers have sought, thus far without success, chip carriers which: (1) exhibit relatively high electrical signal propagation speeds; (2) accomodate relatively high I/O chips while avoiding the need for mechanically drilled holes to interconnect different layers of fan-out circuitry; (3) exhibit a relatively short "time of flight"; and (4) exhibit a relatively high rate of heat dissipation.